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RTL to GDSII: the journey of a chip, step by step

Every chip starts as code and ends as a layout file sent to the foundry. Here's what happens in between.

BhavCore Team7 min read
Iridescent dies on a silicon wafer
Fig. 1: Every design ends up as dies on a silicon wafer.

When people hear "chip design", they often picture a single activity. In reality, a chip passes through a long, carefully engineered sequence of stages, collectively called the RTL-to-GDSII flow. Understanding this flow is the single most useful thing a new VLSI engineer can learn, because every job role in the industry maps to one part of it.

  1. Spec
  2. RTL
  3. Simulation
  4. Synthesis
  5. Floorplan
  6. Placement
  7. CTS
  8. Routing
  9. STA
  10. GDSII
Fig. 2: The ten stages of the RTL-to-GDSII flow.

1. Specification & architecture

It starts with what the chip must do: its functions, performance targets, power budget and interfaces. Architects break the system into blocks and define how they communicate.

2. RTL design

Designers describe each block's behaviour at the Register Transfer Level (RTL) using Verilog, SystemVerilog or VHDL. Good RTL is not just functionally correct. It must also be synthesizable and written with timing, area and power in mind.

3. Verification

Before anything is built, the RTL must be proven correct. Verification engineers build testbenches with SystemVerilog and UVM, write assertions, measure coverage and hunt for bugs. On many projects verification takes more effort than design itself, which is why it is the largest hiring segment in VLSI.

Fig. 3: Simulation waveforms from a UART testbench. The cursor marks the start bit.

4. Synthesis

Synthesis tools translate RTL into a gate-level netlist built from standard cells in a target technology library, guided by timing constraints written in SDC.

5. Physical design

Now the netlist becomes a physical layout:

  1. Floorplanning: deciding where major blocks, I/Os and power grids go.
  2. Placement: positioning millions of standard cells.
  3. Clock tree synthesis (CTS): distributing the clock with minimal skew.
  4. Routing: connecting everything with metal wires across many layers.
Colourful close-up of a silicon die
Fig. 4: A die up close, with its placed and routed blocks catching the light.

6. Sign-off

Before tapeout, the design must pass static timing analysis (STA), power and IR-drop analysis, and physical verification: DRC (design rule check) and LVS (layout versus schematic).

7. GDSII & tapeout

The final layout is exported as a GDSII (or OASIS) file and sent to the foundry. That moment is called tapeout, and it's the milestone every chip team works toward.

Workers in protective suits inside a cleanroom
Fig. 5: After tapeout, fabrication happens in cleanrooms like this one.

Learn it hands-on: with open-source PDKs and EDA tools, students can now take a real design through this entire flow. That's the heart of our Full-Stack Digital VLSI Design programme.

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